1) Field of the Invention
The present invention relates to a processor debugging apparatus and a processor debugging method for scanning and reading a latch in a processor, and more particularly, to a processor debugging apparatus and a processor debugging method that can grasp a sequential transition of a signal in a processor to improve a debugging efficiency.
2) Description of the Related Art
Recently, the integration scale of a processor is increasing and the logics inside the processor are becoming more complex. The complication of logics makes a debugging work of the processor difficult, and makes the debugging time longer. Therefore, various measures are taken to improve the debugging efficiency of the processor.
One of the measures is a scheme of adding a scan circuit to a latch in a processor compatible with the JTAG (Joint Test Action Group) and reading information from the latch (for the JTAG, see IEEE 1349.1 “Test Access Port and Boundary Scan Architecture”, IEEE Standard). In this scheme, the status of the processor can be recognized from outside by examining scanned values, thereby increasing the debugging efficiency. However, the examination of the scanned values merely detects the status of one clock timing and therefore the sequential transition of a signal in the processor cannot be recognized, and as a result, it is difficult to analyze a timing failure that may occur due to a relation between before and after the signal value.
In order to solve the problem, a designer adds, in advance, a processor with a circuit that records signals important for examination in an exclusive random access memory (RAM) at every timing, and examines the values of a plurality of past cycles recorded in the RAM. The amount of information to be recorded and the number of clocks vary depending on the capacity of the used RAM, but several hundred cycles of information are recorded to demonstrate an effect in debugging a timing failure.
However, since the recording capacity of a RAM is determined to, for example, 1 kilobit (Kb), 2 Kb, a designer mounts debugging mechanisms more than the number of signals actually needed and adds a diagnosis circuit to test the operation of the RAM itself. This increases the circuit scale, the number of design steps, and eventually the cost.
Since the RAM is configured by exclusive micro-scale transistors, it is prone to generate problems in fabrication as compared with logics. The mounting of the RAM only for the debugging leads to reduction in the yield of a large scale integration (LSI).
Therefore, the RAM for the debugging purpose is used only at a location where 100 cycles of information are needed for debugging, such as a command control unit or a memory control unit. Such a RAM is not provided in an operation executing unit or the like that does not need 100 cycles of information, and debugging is executed only with latch scanned information alone.
However, with only the scanned information, the operation of the operation executing unit is predicted only from the status of a timing of the information, so that the sequential transitional statuses of the internal circuits of the operation executing unit cannot be recognized, which makes the debugging work of the operation executing unit difficult.